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UID:submissions.supercomputing.org_SC21_sess205_tut122@linklings.com
SUMMARY:Productive Parallel Programming for FPGA with High-Level Synthesis
DESCRIPTION:Tutorial\n\nProductive Parallel Programming for FPGA with High
 -Level Synthesis\n\nde Fine Licht, Hoefler\n\nEnergy efficiency has become
  a first-class citizen in the design of large computing systems.  Spatial 
 architectures, such as FPGAs, promise another major step in energy efficie
 ncy, constituting a middle ground between software programmable architectu
 res and custom-built ASICs.  This tutorial shows how high-level synthesis 
 can be harnessed to productively achieve scalable pipeline parallelism on 
 FPGAs.  Attendees will learn how to target FPGA resources from high-level 
 C++ or OpenCL code, guiding the mapping from imperative code to hardware a
 nd enabling them to develop massively parallel designs with real performan
 ce benefits.  We treat well-known examples from the software world, relati
 ng traditional code optimizations to both corresponding and new transforma
 tions for hardware, building on existing knowledge when introducing new to
 pics.  By bridging the gap between software and hardware optimization, our
  tutorial aims to enable developers from a larger set of backgrounds to st
 art tapping into the potential of FPGAs with real high-performance codes.\
 n\nTag: In-Person Only, Accelerator-based Architectures, Parallel Programm
 ing Languages and Models\n\nRegistration Category: Tutorial Reg Pass
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