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DTSTAMP:20211207T055352Z
LOCATION:Second Floor Atrium
DTSTART;TZID=America/Chicago:20211117T083000
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UID:submissions.supercomputing.org_SC21_sess255_drs108@linklings.com
SUMMARY:TIGRA: A Tightly Integrated Generic RISC-V Accelerator Interface
DESCRIPTION:Doctoral Showcase, Posters\n\nTIGRA: A Tightly Integrated Gene
 ric RISC-V Accelerator Interface\n\nGreen, Smith\n\nField programmable gat
 e array (FPGA) usage in HPC applications is growing with the need for ener
 gy efficient and application specific accelerators. Currently, FPGAs are u
 sed to accelerate algorithms using OpenCL with communication over a CPU bu
 s (loosely coupled accelerators) or by modifying existing architectures to
  incorporate custom logic directly with a CPU (tightly coupled accelerator
 s). However, only the loosely coupled paradigm is feasible to support a va
 riety of acceleration. In this work, we introduce TIGRA, a zero latency in
 terface designed to provide the benefit of tightly coupled FPGA accelerato
 rs without the developer burden of modifying the underlying architecture, 
 which can enable their usage in HPC. TIGRA is demonstrated on the simple P
 icoRV32 RISC-V processor as a proof of concept for the interface. This is 
 also extended to the Rocket Chip Generator, a very feature robust CPU gene
 rator that more closely resembles processors found in modern HPC systems. 
 Both of these designs are tested by implementing the PACoGen Posit arithme
 tic core generator and OpenCores tiny_aes 128-bit encryption designs in th
 e custom logic connected to the TIGRA interface. Each design verifies that
  TIGRA adds 0 latency when executing in the CPU pipeline. Further verifica
 tion was completed on AWS F1 instances with FPGAs to prove the functionali
 ty on hardware beyond simulation.\n\nTag: In-Person Only\n\nRegistration C
 ategory: Tech Program Reg Pass, Exhibit Hall Only
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