HiPar21: 2nd Workshop on Hierarchical Parallelism for Exascale Computing
Event Type
TimeSunday, 14 November 20219am - 5:30pm CST
DescriptionHigh-performance computing (HPC) platforms are evolving towards having fewer but more powerful nodes, driven by the increasing number of physical cores in multiple sockets and accelerators. The boundary between nodes and networks is starting to blur, with some nodes now containing tens of compute elements and memory sub-systems connected via a memory fabric. The immediate consequence is an increasing complexity, due to ever-more complex architecture (e.g., memory hierarchies), novel accelerator designs and energy constraints. Spurred largely by this trend, hierarchical parallelism is increasingly gaining momentum. This approach embraces the intrinsic complexity of current and future HPC systems, rather than avoiding it, by exploiting parallelism at all levels: compute, memory and network. This workshop focuses on hierarchical parallelism. It aims at bringing together application, hardware and software practitioners proposing new strategies to fully exploit computational hierarchies, and provides examples to illustrate their benefits to achieve extreme scale parallelism.
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