A Framework for Customizable FPGA-based Image Registration Accelerators
TimeMonday, 15 November 20212:30pm - 3pm CST
DescriptionImage Registration is a highly compute-intensive optimization procedure that determines the geometric transformation to align a
floating image to a reference one. Generally, the registration targets
are images taken from different time instances, acquisition angles,
and/or sensor types. Several methodologies are employed in the
literature to address the limiting factors of this class of algorithms,
among which hardware accelerators seem the most promising solution to boost performance. However, most hardware implementations are either closed-source or tailored to a specific context,
limiting their application to different fields. For these reasons, we
propose an open-source hardware-software framework to generate
a configurable architecture for the most compute-intensive part of
registration algorithms, namely the similarity metric computation.
This metric is the Mutual Information, a well-known calculus from
the Information Theory, used in several optimization procedures.
Through different design parameters configurations, we explore
several design choices of our highly-customizable architecture and
validate it on multiple FPGAs. We evaluated various architectures
against an optimized Matlab implementation on an Intel Xeon
Gold, reaching a speedup up to 2.86×, and remarkable performance
and power efficiency against other state-of-the-art approaches.