Designing a Streaming Data Coalescing Architecture for Scientific Detector ASICs with Variable Data Velocity
TimeFriday, 19 November 20219:20am - 9:40am CST
DescriptionScientific detectors are a key technological enabler for many disciplines. Application-specific integrated circuits (ASICs) are used for many of these scientific detectors. Until recently, pixel detector ASICs have been used mainly for analog signal processing of the charge from the sensor layer and the transmission of raw pixel data off the detector ASIC. However, with the availability of more advanced ASIC technology nodes for scientific application, more digital functionality from the computing domains (e.g., compression) can be integrated directly into the detector ASIC to increase data velocity. However, these computing functionalities often have high and variable latency, whereas scientific detectors must operate in real-time (i.e., stall-free) to support continuous streaming of sampled data. This paper presents an example from the domain of pixel detectors with on-chip data compression for X-ray science applications. To address the challenges of variable-sized data from a parallel stream of compressors, we present an ASIC design architecture to coalesce variable-length data for transmission over a fixed bit-width network interface.