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PPIR: Parallel Pattern Intermediate Representation
Event Type
Workshop
Tags
Online Only
Algorithms
Architectures
Extreme Scale Comptuing
Heterogeneous Systems
Memory Systems
Parallel Programming Languages and Models
Resource Management and Scheduling
Registration Categories
W
TimeSunday, 14 November 20214pm - 4:30pm CST
LocationOnline
DescriptionHPC systems are becoming rapidly larger, heterogeneous, and generally more complex to fulfill the growing demand for computational resources in science and engineering. HPC system and architecture-specific optimizations are necessary to leverage the full potential of such systems. One approach is to develop a high-level, structured source code by leveraging parallel patterns. Our previous work proposed a framework to optimize pattern-based codes for a target HPC system automatically. Global optimizations can be carried out by the framework, optimizing the dataflow throughout the parallel algorithm and efficiently scheduling the application on the available resources.

We propose a compact and fast intermediate representation (IR) of parallel pattern-based applications to enable such global optimizations. A tree-based hierarchical abstraction called abstract pattern tree (APT) is introduced to this end. It is augmented with scheduling information provided by the optimization framework. The resulting IR is implemented in a prototype compiler and evaluated on the Rodinia benchmark suite. 17 out of the 19 benchmarks could be represented by a small set of parallel patterns and statically analyzed by the prototype compiler. The original source code could be highly condensed by using parallel patterns, which increases the development productivity. The compiler prototype implementation showed a feasible compilation time below one second for most benchmarks. The proposed PPIR was compared to LLVM IR.
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