SC21 Proceedings

The International Conference for High Performance Computing, Networking, Storage, and Analysis

Successful FPGA Programming Methods and Tools for HPC


Authors: Martin Herbordt (Boston University), Kentaro Sano (RIKEN), Christian Plessl (Paderborn University, Germany), Jeffrey Vetter (Oak Ridge National Laboratory (ORNL)), Kazutomo Yoshii (Argonne National Laboratory (ANL)), Taisuke Boku (University of Tsukuba), Torsten Hoeffler (ETH Zürich), Venkata Krishnan (Intel Corporation)

Abstract: FPGAs have gone from niche components to being a central part of many data centers worldwide, and are now being considered for core HPC installations. While it is generally agreed that what has prevented more widespread use of FPGAs is programmability, vendors and the wider community have recently made tremendous progress: FPGAs for general HPC is apparently within reach. This BOF has two parts. The first is a series of lightning talks presenting new tools and methods. The second is a general discussion driven by the interests of the attendees and potentially including additional topics.

Long Description: In the past five years, FPGAs have gone from niche components to being a central part of many data centers worldwide and are now being considered for integration into future-generation core HPC installations. But while current use cases often match those of traditional accelerators (e.g., AWS), most of the millions of newly deployed FPGAs are in other configurations such as smart NICs, network-attached bump-in-the-wire processors, and in storage architectures. While it is generally agreed that what has prevented more widespread use of FPGAs as traditional HPC accelerators is programmability, vendors and the wider community have recently made tremendous progress, and the use of FPGAs for general HPC is apparently within reach.

The topic of this BOF is successful FPGA programming methods and tools for HPC. Areas to be covered include projected workloads; programming productivity (languages, models, environments); likely node architectures (CGRA, coherence, compute accelerator, network accelerator, storage accelerator); and communication models and support (MPI-like message passing, RDMA/Libfabric-like one sided communication, point-to-point streaming connections).

There are multiple goals of this BOF. First is communication of current and projected methods to a broad HPC audience. Second is obtaining feedback from the same. Third is expert discussion and evaluation of current methods. Fourth is to identify best practices that could become the basis for standards. Fifth is to provide a forum for the HPC/FPGA community to review status and present breaking news and emerging topics.

The relevance to a general HPC audience is filling the knowledge/experience gap with respect to FPGAs in HPC. While most SC attendees are familiar with the basics of FPGAs, few have used them in production, and only a tiny fraction have had such experience recently. Since FPGAs are already widespread in data centers, and are being considered for more prominent roles, bridging this gap is vital.

We are extremely proud that, aside from last year, this BOF has run continuously since 2010. In the early years the emphasis was on outreach, novel architectures, and niche applications, and had 50-70 attendees per year. More recently there has been additional emphasis on the emerging large deployments and attendance now regularly approaches 100.

The expected outcomes are satisfying the goals stated, especially in showcasing FPGA/HPC to a broader audience, and in identifying best practices.

Since its inception, this BOF has been the go-to meeting place for the FPGA-in-HPC community, not just at SC, but in the yearly calendar. The community has grown tremendously and there is now a series of international workshops on FPGAs for HPC. This BOF is complementary to other major FPGA event at SC--the H2RC workshop—in that it focuses on systems and standards rather than research or use cases.

All session leaders have strong experience in HPC, reconfigurable computing, or both. We will select multiple speakers from session leaders and leading experts in academia, government, and industry.

Audience participation is a key success metric, and half the time has been allocated for discussion. As always, we expect the conversation to be lively and informative.


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