MCHPC’21 Afternoon Invited Talk: New Trends for sPIN-Based In-Network Computing - from Sparse Reductions to RISC-V Acceleration

Workshop:MCHPC’21: Workshop on Memory Centric High Performance Computing

Authors: Torsten Hoefler (ETH Zürich)

Abstract: Accelerated in-network computations promise significant optimizations ranging from data-movement reductions to specialization opportunities in processing elements. We show updates within the sPIN (streaming Processing in the Network) network accelerator programming model - the "CUDA for networking". There, we demonstrate 2x lower required bandwidth for (sparse) reductions and a highly-optimized packet processing design based on a low-power RISC-V multi-core architecture.

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