The International Conference for High Performance Computing, Networking, Storage, and Analysis
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Workshop:LLVM-HPC2021: The Seventh Workshop on the LLVM Compiler Infrastructure in HPC
Authors: John Leidel, Ryan Kabrick, and David Donofrio (Tactical Computing Laboratories)
Abstract: The many nuances associated with hardware development have fostered a development environment exclusive to those possessing extensive knowledge on the low-level implementation details necessary for an effective design. Allowing users to focus on the design aspects specific to the domain they work in by abstracting the low-level implementation details could prove invaluable to their success
This work describes the StoneCutter infrastructure, along with its encompassing OpenSoC System Architect suite of tools, provide users with a high-level, C-like syntax for rapidly designing ISAs. The compiler is responsible for ingesting instruction definitions and generating optimized Chisel HDL output as well as target-specific LLVM-linked compiler capable of executing binaries on the prototype ISA. During the codegen phase, the necessary control signals are subsequently generated and then used to automatically pipeline the entire ISA based on the design's I/O, arithmetic operations, and flow-control.