The International Conference for High Performance Computing, Networking, Storage, and Analysis
The International Conference for High Performance Computing, Networking, Storage, and Analysis
Workshop:LLVM-HPC2021: The Seventh Workshop on the LLVM Compiler Infrastructure in HPC
Authors: sandya mannarswamy and dibyendu Das (Intel Corporation)
Abstract: Instruction combiner (IC) is a critical optimization pass, which replaces a sequence of instructions with an equivalent and optimized instruction sequence at basic block level. There can be thousands of IC patterns which need to be frequently updated as new coding styles/applications evolve over time. This makes the IC optimization pass error prone. To mitigate these challenges of traditional IC, we design a Neural Instruction Combiner (NIC) and demonstrate its feasibility by integrating it into the LLVM compiler pipeline. NIC leverages neural machine translation seq2seq model technique for generating optimized encoded IR sequence from the unoptimized encoded IR sequence. We improve the standard attention mechanism with a compiler guided attention approach. To the best of our knowledge, ours is the first work demonstrating the feasibility of a neural instruction combiner for LLVM. Our early results show that NIC can achieve Bleu precision of 0.94 and exact match accuracy of 0.83.