TIGRA: A Tightly Integrated Generic RISC-V Accelerator Interface

Author: Brad Green (Clemson University)

Advisor: Melissa C. Smith (Clemson University)

Abstract: Field programmable gate array (FPGA) usage in HPC applications is growing with the need for energy efficient and application specific accelerators. Currently, FPGAs are used to accelerate algorithms using OpenCL with communication over a CPU bus (loosely coupled accelerators) or by modifying existing architectures to incorporate custom logic directly with a CPU (tightly coupled accelerators). However, only the loosely coupled paradigm is feasible to support a variety of acceleration. In this work, we introduce TIGRA, a zero latency interface designed to provide the benefit of tightly coupled FPGA accelerators without the developer burden of modifying the underlying architecture, which can enable their usage in HPC. TIGRA is demonstrated on the simple PicoRV32 RISC-V processor as a proof of concept for the interface. This is also extended to the Rocket Chip Generator, a very feature robust CPU generator that more closely resembles processors found in modern HPC systems. Both of these designs are tested by implementing the PACoGen Posit arithmetic core generator and OpenCores tiny_aes 128-bit encryption designs in the custom logic connected to the TIGRA interface. Each design verifies that TIGRA adds 0 latency when executing in the CPU pipeline. Further verification was completed on AWS F1 instances with FPGAs to prove the functionality on hardware beyond simulation.

Thesis Canvas: pdf

Back to Doctoral Showcase Archive Listing