Seventh International Workshop on Heterogeneous High-Performance Reconfigurable Computing
TimeMonday, 15 November 20219am - 5:30pm CST
DescriptionAs conventional vonNeumann architectures are suffering from rising power densities, we are facing an era with power, energy efficiency and cooling as first-class constraints for scalable HPC. FPGAs can tailor the hardware to the application, avoiding overheads and achieving higher hardware efficiency than general-purpose architectures. Leading FPGA manufacturers have recently made a concerted effort to provide a range of higher-level, easier-to-use high-level programming models for FPGAs, and much of the work in FPGA-based deep learning is built on these frameworks.
Such initiatives are already stimulating new interest within the HPC community around the potential advantages of FPGAs over other architectures. With this in mind, this workshop, now in its fifth year, brings together HPC and heterogeneous-computing researchers to demonstrate and share experiences on how newly-available high-level programming models are already empowering HPC software developers to directly leverage FPGAs, and to identify future opportunities and needs for research in this area.