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Multilevel Simulation-Based Co-Design of Next Generation HPC Microprocessors
Event Type
Online Only
Accelerator-based Architectures
Computational Science
Emerging Technologies
Extreme Scale Comptuing
File Systems and I/O
Heterogeneous Systems
Parallel Programming Languages and Models
Scientific Computing
Software Engineering
Registration Categories
TimeMonday, 15 November 202110:30am - 11am CST
DescriptionThis paper demonstrates the combined use of three simulation tools in support of a full co-design methodology for an HPC-focused SoC. The simulation tools make different trade-offs among simulation speed, accuracy and model abstraction level, and are shown to be complementary to one another. We apply the MUSA trace-based simulator for the initial sizing of vector register length, SLC size and memory bandwidth. It has proven to be very efficient at pruning the design space, as its models enable good enough accuracy without the need to resort to highly detailed simulations.

Then we apply gem5, a cycle-accurate microarchitecture simulator, for a more refined analysis of the performance potential of our reference SoC architecture, with models able to capture detailed hardware behavior at the cost of simulation speed. Furthermore, we study NoC topology and IP placements using both gem5 for representative small- to medium-scale configurations and SESAM/VPSim, a transaction-level emulator for larger scale systems with good simulation speed and sufficient architectural details.

Overall, we consider several system design concerns, such as processor subsystem sizing and NoC settings. We apply the selected simulation tools, focusing on different levels of abstraction, to study several configurations with various design concerns, and evaluate them to guide architectural design and optimization decisions. Performance analysis is conducted with a number of representative benchmarks. The obtained numerical results provide guidance and hints to designers regarding SVE register length, SLC sizing and memory bandwidth, as well as the best placement of memory controllers and NoC form factor. Thus, we provide critical insights for efficient design of future HPC microprocessors.
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