MCHPC’21 Afternoon Invited Talk: New Trends for sPIN-Based In-Network Computing – from Sparse Reductions to RISC-V Acceleration
Presenter
Event Type
Workshop
Online Only
Architectures
Memory Systems
Parallel Programming Languages and Models
System Software and Runtime Systems
W
TimeSunday, 14 November 20212pm - 3pm CST
LocationOnline
DescriptionAccelerated in-network computations promise significant optimizations ranging from data-movement reductions to specialization opportunities in processing elements. We show updates within the sPIN (streaming Processing in the Network) network accelerator programming model - the "CUDA for networking". There, we demonstrate 2x lower required bandwidth for (sparse) reductions and a highly-optimized packet processing design based on a low-power RISC-V multi-core architecture.
Presenter
