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Workshop: H2RC: Seventh International Workshop on Heterogeneous High-Performance Reconfigurable Computing
Event TypeWorkshop
Tags
Accelerator-based Architectures
Applications
Architectures
Emerging Technologies
Heterogeneous Systems
Memory Systems
Networks
Registration Categories
W
TimeMonday, 15 November 20219am - 5:30pm CST
Location231-232
Presentations
9:00am - 9:01am CSTSeventh International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC)
9:01am - 9:05am CSTH2RC 2021: Opening Remarks
Presenter
9:05am - 10:00am CSTHardware Specialization for Efficiency and Performance
Presenter
10:00am - 10:30am CSTH2RC: Morning Break (10-10:30)
10:30am - 11:00am CSTACCL: FPGA-Accelerated Collectives over 100 Gbps TCP-IP
11:00am - 11:30am CSTNear-Data FPGA-Accelerated Processing of Collective and Inference Operations in Disaggregated Memory Systems
Author/Presenters
11:30am - 12:00pm CSTEfficient HW and SW Interface Design for Convolutional Neural Networks Using High-Level Synthesis and TensorFlow
12:00pm - 12:30pm CSTOptimizing a Hardware Network Stack to Realize an In-Network ML Inference Application
12:30pm - 2:00pm CSTH2RC: Lunch Break (12:30-2)
2:00pm - 2:30pm CSTOptimized Implementation of the HPCG Benchmark on Reconfigurable Hardware
Author/Presenter
2:30pm - 3:00pm CSTA Framework for Customizable FPGA-based Image Registration Accelerators
Author/Presenter
3:00pm - 3:30pm CSTH2RC: Afternoon Break (3-3:30)
3:30pm - 3:45pm CSTThe Open Cloud Testbed: A Resource for FPGA and Cloud Researchers
Presenter
3:45pm - 4:15pm CSTEnhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components
Author/Presenter
4:15pm - 4:30pm CSTDevice_global: A SYCL Extension Introducing Device-Scoped Allocations to Enhance Performance and Usability
4:30pm - 5:00pm CSTPortable Compilation of NumPy to FPGAs
5:00pm - 5:30pm CSTPorting In-Compressible Flow Matrix Assembly to FPGAs for Accelerating HPC Engineering Simulations
Author/Presenter
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