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Remote Participation
Device_global: A SYCL Extension Introducing Device-Scoped Allocations to Enhance Performance and Usability
Event Type
Accelerator-based Architectures
Emerging Technologies
Heterogeneous Systems
Memory Systems
Registration Categories
TimeMonday, 15 November 20214:15pm - 4:30pm CST
DescriptionField programmable gate arrays (FPGAs) are increasingly targeted by high level programming languages including C++, OpenCL, SYCL, and DPC++. Device-side language constructs are often designed first to target graphics processing units (GPUs) due to their proliferation, so there are design gaps to fill when enhancing languages to target reconfigurable architectures. One key gap in the SYCL specification is the ability to declare memory shared between kernels or functions on a single device, which can be implemented using efficient on-chip reconfigurable memory resources of an FPGA.

This talk will describe a new language extension for DPC++ that will subsequently be proposed for the next SYCL specification, and which enables device-scope memory allocations that are accessed like they are global variables. This feature is important for spatial architectures in two ways: (1) it enables construction and additional optimization using on-chip memory resources; and (2) allows semantics to be defined around reprogramming and initialization of data in an efficient way for reconfigurable architectures.

The talk will detail the semantics and optimization opportunities enabled by the extension, aspects of lifetime and initialization, controls enabling optimization on FPGA (both hints and semantic modifiers), and divergence from the existing OpenCL/SPIR-V program/module scope variable features. These benefits combine to close a recurring gap in the device language across architectures. The device_global feature enables both performance and usability in common coding patterns, and is the result of significant work that aims to inform the next version of the SYCL specification.
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